module D_mem_tb;

  reg clk;
  reg [31:0] Data_in, Addr;
  reg MemWr, rst;
  
  wire [31:0] Data_out;
  
  initial begin
    clk = 0;
    repeat (8) begin   //set clock 
      #5 clk = ~clk;
    end
  end
  //get D_mem  module
  D_mem dut (
    .Data_in(Data_in),
    .MemWr(MemWr),
    .Addr(Addr),
    .clk(clk),
    .rst(rst),
    .Data_out(Data_out)
  );
  
  // get a radom Data_in
  initial begin
    #5
    rst = 1'b0;
    MemWr = 1'b1;
    Data_in = $random;
    Addr = $random & 32'h00000fff; // 4KB address range
    
    #15
    rst = 1'b0;
    MemWr = 1'b0;
  end
   initial begin
    $dumpfile("D_mem_wave.vcd");
    $dumpvars(0,D_mem_tb);
  end
    
endmodule